2022-12-21 11:19:35 So, in my x86 nasm system, I have those variants of my conditional returns that allow me to do have an implicit 0 argument on the conditionals, and also those variants that allow me to retain one argument that would otherwise be popped. 2022-12-21 11:21:29 I don't have enough opcodes to implement all of those "explicitly" in the system, but I'd also rather not have to do a lot of ugly manipulations to get those effects. It probably makes sense to have a 0 instruction that lets me push a zero with just one instruction slot, and the other word that would make it easy to get the whole set of effects would be a word that dups the next on stack item. Does that 2022-12-21 11:21:31 word have a standard name? 2022-12-21 11:22:00 Implementation-wise it would just push NOS to the RAM stack, just as tuck pushes TOS to the ram stack. 2022-12-21 11:22:47 over swap does it, and isn't TOO bad. 2022-12-21 12:04:52 would it make sense to profile? some clever things taking up an instruction slow may not make much of a difference in practice 2022-12-21 12:05:00 slow=slot 2022-12-21 12:15:33 Yeah, I'm holding off on some of those things. They can always be added later if it makes sense. 2022-12-21 12:16:05 Focusing right now on just getting the core circuitry to run through the right flow. 2022-12-21 12:17:42 It's enough for me now to see that there is a simple path to the full capability. 2022-12-21 12:18:09 I mean, one could always use 0 literals and over swap to get the effect. 2022-12-21 12:18:30 Adding more should be only if I decide that brute force way of doing it isn't acceptable. 2022-12-21 12:22:28 Another optimization I won't worry about for now is the "skipping over" of trailing nop's in a cell. If all remaining slots or nop, ideally you'd just go straight for the next cell. But it will be simpler getting it to work to just grind through all five cells, even if that does mean just spinning your wheels. 2022-12-21 12:22:37 s/or/are/ 2022-12-21 12:22:52 "all five slots" 2022-12-21 15:30:23 hi 2022-12-21 15:30:25 Hi 2022-12-21 15:30:56 does anybody know if it is possible to get an ammeter or wattmeter that works with higher source frequencies, like up to 1 Mhz 2022-12-21 15:33:16 Am wondering about measuring the current in a circuit if source or signal is not 60Hz like the DMMs want 2022-12-21 15:48:50 you may want a scope? 2022-12-21 16:02:51 decay: scopes only work for measuring voltage, I think...? 2022-12-21 16:03:33 lispmacs[work]: current shunt and a sillyscope 2022-12-21 16:03:54 lispmacs[work]: what exactly are you trying to measure? 2022-12-21 16:05:44 gordonjcp: I'm interesting in figuring out the impedances of components at arbitrary frequencies, though I didn't really want an LCR meter that just magically does it for me 2022-12-21 16:06:09 lispmacs[work]: a dual-trace 'scope will be instructive 2022-12-21 16:06:35 measure your genny output with one trace and your load current with the other 2022-12-21 16:07:02 gordonjcp: genny? 2022-12-21 16:07:13 signal generator 2022-12-21 16:07:23 and to measure the load current? 2022-12-21 16:07:42 like I said, use a current shut 2022-12-21 16:07:44 *shunt 2022-12-21 16:08:21 basically a low-value non-inductive resistor 2022-12-21 16:08:57 and even better if you use the voltage and current as an XY plot 2022-12-21 16:10:09 gordonjcp: but even the so called non-inductive resistors end up having inductance as the frequency goes up, right? 2022-12-21 16:12:17 gordonjcp: so, the current shunt is for measuring the voltage drop across the resistor, right? 2022-12-21 16:16:33 yes 2022-12-21 16:16:36 look at this 2022-12-21 16:16:39 https://tinyurl.com/2ptlwjwo 2022-12-21 16:16:39 Everything has *some* inductance and *some* capacitance. 2022-12-21 16:16:51 Wire-wound resistors are the ones to stay away from if you want to minimize inductance. 2022-12-21 16:17:07 tbh even if they have inductance their Q is the square root of fuck all 2022-12-21 16:17:08 jarheads are pretty low on capacitance 2022-12-21 16:17:17 thinfilm grafite resistors too? 2022-12-21 16:17:20 If current flows, it makes a magnetic field, and that's what inductance relates. 2022-12-21 16:17:33 If charge is present, there's an electric field, and that's what capacitance relates. 2022-12-21 16:17:43 I got bitched at endlessly for using wirewound resistors as the cathode resistors in an HF valve PA 2022-12-21 16:17:46 but 2022-12-21 16:18:25 Putting the two conductors as close together as possible (or better yet, twising them - "twisted pair") minimizes the magnetic field, since the opposing currents at almost the same place make fields that cancel out. 2022-12-21 16:18:29 they're 4.7Ω 10W resistors, they're a few turns of very thick wire, and they're bypassed by four 0.1μF capacitors across the two valve bases 2022-12-21 16:18:42 there's not a sniff of RF across them, there's barely audio across them 2022-12-21 16:18:57 and at very very very low frequencies like up to 30MHz 2022-12-21 16:19:01 which is basically DC 2022-12-21 16:19:08 Heh. 2022-12-21 16:19:09 they have no appreciable inductance 2022-12-21 16:19:13 Tell that to a ham radio operator. 2022-12-21 16:19:23 73 de MM0YEQ 2022-12-21 16:19:33 "Up to 30 MHz" is a most of their world. 2022-12-21 16:19:39 I use HF a lot 2022-12-21 16:19:44 but the real fun is in microwave 2022-12-21 16:19:47 WV5F here. 2022-12-21 16:19:49 not that 5.8GHz longwave shit 2022-12-21 16:19:56 60GHz or bust 2022-12-21 16:20:01 :-) 2022-12-21 16:20:09 if you're not tuning the aerial with jeweller's rouge are you even doing radio? 2022-12-21 16:20:09 I'm horribly inactive, though. 2022-12-21 16:21:08 I started out decades ago with a Tech license, then a couple years ago decided to upgrade "just because I could." The technical aspects were no problem, and there's no longer any code requirement - that had always been my obstacle. 2022-12-21 16:21:44 I want to get back into doing packet on VHF 2022-12-21 16:21:51 I reckon I've got a good path up to my mate's house from here 2022-12-21 16:22:48 50 miles give or take, not a totally obstructed path 2022-12-21 16:24:47 gordonjcp: for the low-inductance shunt resistor, would you recommend something I could buy from Amazon? I'm having trouble figuring out which ones are the low-inductance 1 ohm resistors 2022-12-21 16:25:20 My most recent interest has been QRP on the low frequency bands. 2022-12-21 16:25:38 yeah, any low-value resistor you have lying around 2022-12-21 16:25:41 With stuff I make myself. 2022-12-21 16:25:41 KipIngram: yeah QRP is good 2022-12-21 16:26:01 I like how much voice you can stuff i to FreeDV 2022-12-21 16:26:04 they all seem to be wirewound 2022-12-21 16:26:19 but not sure how they are wound 2022-12-21 16:26:23 I did some QRP CW on 5MHz with an Adret signal genny, BFY51 and a tank coil as a PA developing about 1W, and a homebrew SDR 2022-12-21 16:26:29 for how little bandwidth it requires. 2022-12-21 16:26:34 lispmacs[work]: what have you got lying about? 2022-12-21 16:26:52 I should fix my SDR to work in modern Linux 2022-12-21 16:28:11 I've got some 16 ohm 100W resistors, which somebody told me are supposed to be non-inductive 2022-12-21 16:29:03 looks like I've got some 2.7 ohm carbon resistors 2022-12-21 16:29:30 5mm diameter, 12mm length, axial 2022-12-21 16:29:55 That geometry is good for inductance. For low inductance I mean. Just straight through - no loops. 2022-12-21 16:36:02 2.7 ohm carbon will be fine, probably good for up to about .25W or so 2022-12-21 17:10:07 are the little DIP inductors supposed to be linear inductance across frequencies? I'm my experiments, this 820 uH inductor gives twice as much impedance as it is supposed to at 10kH, but comes to about the expected value of impedance at 40kH 2022-12-21 17:10:47 wondering if that is due to a property of the inductor, or an artifact of my testing 2022-12-21 20:27:57 They can vary in frequency; that's usually because there is some capaictance there too and it becomes more important at higher frequencies. 2022-12-21 20:28:37 And you're talking about a very wide frequency range there, given that you're down near zero. 2022-12-21 20:29:06 I.e., 40 kHz = four times 10 kHz. 2022-12-21 20:29:34 Whereas up at say 1 MHz, a 30 kHz shift would be more or less negligible. 2022-12-21 20:30:35 If you've got a data sheet it should have graphs and so on so you know what to expect. 2022-12-21 20:32:48 What is it you're trying to make? Filters or something? 2022-12-21 21:09:50 Looks like there are ten sources in this processor that the top of stack can get loaded from. That should be the only really heavy one - the other registers will have quite a bit fewer sources, I'm guessing. 2022-12-21 21:10:07 And that's counting "ALU" as as single source. 2022-12-21 21:11:30 I could get it down to eight if I took the same limitations Chuck took in the F21. He has those "address registers," but he only allows one of them to be transferred BACK to the stack. 2022-12-21 21:11:52 Getting it down to eight has a good bit of value, though. 2022-12-21 21:15:29 I only have 13 ALU ops defined, though, so there are three more paths that could run through thhere. 2022-12-21 21:16:04 That's not going to get down to eight, so a 16:1 mux is going to be unavoidable there. 2022-12-21 22:27:46 You know, I won't try to do this initially, but it occurs to me that it might be possible to speed this design up considerably if I disallow slot 0 from calling out a ALU operation. If that restriction holds, then that one 4-1 level of that 16-1 selection process could go when the ALU instruction is in slot 1. The registers on the output of those 4-1 muxes would catch and hold those interim results. This 2022-12-21 22:27:48 would happen during the cycle before that instruction's actual cycle. Then the real active cycle would 4-1 select one of of those interim values for clocking into TOS. 2022-12-21 22:28:10 Sort of a "pipelined ALU. 2022-12-21 22:28:35 Might wind up unworkable, because in some situations the data won't be available until the active cycle, so... meh. 2022-12-21 22:28:45 Just having a blue sky moment. :-) 2022-12-21 22:29:27 The six input luts are ideal for 4-1 selection. Then two layers of luts can do 16-1; four 4-1's followed by 4-1. 2022-12-21 22:30:01 So I need to curate this instruction set design until I get it down to 16 data sources total for "next TOS." 2022-12-21 22:31:22 Right now I'm at 17, so... gotta scratch my head some. 2022-12-21 22:32:37 RAM counts as two - it needs to be able to pick up instruction port RAM data for literals, and data port RAM variables for variable reads. 2022-12-21 22:33:17 None of those 17 look nice to give up, though. :-( 2022-12-21 22:33:47 didn't Paramount cancel TOS 2022-12-21 22:33:52 There is an 18th, for loading 0 onto the stack, but I can sneak that in by resetting the flip flops, so it's not in that selection array. 2022-12-21 22:34:25 :-) Jesus, our world would end if TOS got canned. Suddenly every Forth in the world would stop working. 2022-12-21 22:35:38 I've dropped ability to load FROM the address registers at all - right now I have them write-only. 2022-12-21 22:36:07 Which I don't like, but it was an easier decision than giving up anything left now. 2022-12-21 22:37:52 If I can't think of any other way to get to 16 I could always arrange the stack pointer read in a chain. p> would pull sp to the stack and swap sp and rp; another p> would then pull rp to the stack and swap them back. So you'd always do p> in pairs, to keep the stack pointers right. 2022-12-21 22:38:09 So sp@ would be p> p> drop and rp@ would be p> p> nip. 2022-12-21 22:38:21 We don't really use sp@ and rp@ very often, so that's not so bad. 2022-12-21 22:38:41 it was as if a million forths cried out and then whoops wrong show 2022-12-21 22:39:52 If I became desperate to be able to read back the addr regs I could make the chain longer (so more p> ops would be required. I'm not too bothered at the moment, though, by having them read only. 2022-12-21 22:39:56 write only I mean. 2022-12-21 22:41:14 I guess that plan will work for now. 2022-12-21 22:43:38 MrMobius: See, this touches on the value of thinking at this level of design. Two layers of luts vs. three - this is in the critical timing flow. Adding a layer of luts brings the clock rate down, because now the clock period has to "contain" that extra lut delay. When you only have a small number of layers, a one layer change can have a significant percentage affect on your achievable clock rate. 2022-12-21 22:45:50 And in this chip with its 6-input luts, going from 17 possible places to get next TOS to 16 removes that entire extra layer. 2022-12-21 22:46:23 If I were just writing behavioral equations for what I wanted the thing to do, that might not be visible to me in the same way. 2022-12-21 22:48:44 KipIngram: my forth is coming along! i separated the code into "machine code primitives" which is in assembly, "forth primitives" which i hand compiled from forth to lists of cells in the assembly file, and proper forth from a text file 2022-12-21 22:49:01 Nice nice! 2022-12-21 22:49:08 :-) thanks! 2022-12-21 22:49:09 Mine's separated much the same way. 2022-12-21 22:49:31 Used macros to make those bits "prettier." 2022-12-21 22:49:47 code words are, well, nasm code, with a macro call before them to define the name. 2022-12-21 22:49:58 what do you use for an assembler... ah nasm? 2022-12-21 22:50:07 definitions use the dq command - just has a list of the words in the definition. 2022-12-21 22:50:24 I think it's about as pretty as it could be. 2022-12-21 22:50:32 yes that's exactly what i do, except it is in gnu gas instead of nasm 2022-12-21 22:50:38 That's evolved over my last couple of efforts, and gotten a little nicer each time. 2022-12-21 22:50:55 You recall my definition cells are all offsets. 2022-12-21 22:51:22 In the previous version, I had to subtract the base from each one explicitly, so the list was like dq -do, -do, etc. 2022-12-21 22:51:28 This time I got the -do into the macro. 2022-12-21 22:51:44 Which means now when I want a literal number in a definition cell, I have to +do on that. 2022-12-21 22:51:51 But there are a lot fewer of those than the other. 2022-12-21 22:52:16 Since the macro can't tell the difference between what's a word offset and what's a literal value. 2022-12-21 22:52:56 I usually write the Forth for the word as a comment just before that. Then I can stare at it to vet my manual compilation. 2022-12-21 22:52:57 i used a macro in my 8086 version to convert to segment+offset form 2022-12-21 22:53:15 It's nice to get that kind of plumbing "hidden under the hood." 2022-12-21 22:53:29 KipIngram: yes i have a file with the forth versions of the machine code, but it is a separate file.. 2022-12-21 22:53:40 i don't have comments 2022-12-21 22:53:55 except an explanation of how i used the registers at the top of the file 2022-12-21 22:54:05 asm is kinda horrible without comments 2022-12-21 22:54:13 i used BX for top of stack 2022-12-21 22:54:17 I hope I'll eventually be able to just copy those Forth comments out and into blocks when I'm ready to try to recompile the thing in Forth. 2022-12-21 22:54:39 Though I'm sure that in spite of all of my staring there are a few mismatches in there, between the comments and the definition. 2022-12-21 22:54:52 It's hard to keep perfect disipline about always changing the comment when I'm chasing a bug. 2022-12-21 22:55:34 thrig: the primitives are pretty simple .. the names help.. xtPlus: add BX,[SI] ; add SI,2 ; NEXT 2022-12-21 22:55:37 NEXT is a macro 2022-12-21 22:55:57 oh wait not in the 8086 version... in 8086 it is a jump 2022-12-21 22:56:03 So right now my 16 things that can serve as next TOS value are like so: and or not xor + - 1+ 1- 1<< 1>> +* 8<< 8>> ptr tor nos 2022-12-21 22:56:10 xtPlus: add BX,[SI] ; add SI,2 ; jmp NEXT 2022-12-21 22:56:13 ptr is the aforementioned "chain" for sp@ and rp@. 2022-12-21 22:56:52 not can be 0xffff xor 2022-12-21 22:57:48 Another similar "trick" I could play would be to have sp@ and rp@ put the value on the RETURN stack. Then I'd do sp@ r> or rp@ r> to get the desired effect. That may actually be better, and would also more gracefully extend to the address registers. 2022-12-21 22:58:03 Because the return stack top is going to have a LOT fewer sources that TOS. 2022-12-21 22:58:10 That's better. 2022-12-21 22:59:19 Also doesn't require an opcode to read the chain. 2022-12-21 23:00:07 And only takes two opcodes instead of three to get the final result. 2022-12-21 23:01:15 With that idea in mind I now have one "possible TOS result" to spare. 2022-12-21 23:08:53 Oh, and often you want "no change" to TOS, but that can be worked in via the register's clock enable input. 2022-12-21 23:09:10 So "self" doesn't have to be in the list explicitly. 2022-12-21 23:16:33 Oh, the logic slice layout of this particular Xilinx chip (Artix-7) is here: 2022-12-21 23:16:36 https://cse.unl.edu/~jfalkinburg/cse_courses/2020/436/lecture/lecture32.html 2022-12-21 23:16:52 This guy has DSP slices too; maybe later I'll want to look into what those can do. 2022-12-21 23:19:19 KipIngram: i managed to make "accept" be written in forth, which is good because right now it only has backspace for editing the line ... i want to make a much more capable input with arrow keys and everything, and i can write it in forth, not assembly 2022-12-21 23:20:52 and it's not like charles moore said that i would be adding features in case they might be used ... i really want a nice line editor for inputting code 2022-12-21 23:21:09 and a line history 2022-12-21 23:21:27 i would really use it 2022-12-21 23:52:45 Arrow keys are hard, because they come in as multi-char escape sequences. 2022-12-21 23:53:07 I used ctrl-letter keys, a la vim, for my cursor control while editing. 2022-12-21 23:53:10 disabling them surfaced a segfault in vi 2022-12-21 23:53:17 Those are all in the ASCII range 1-26. 2022-12-21 23:53:35 And you don't have to move your hands from home position to use them. 2022-12-21 23:53:53 disabling the arrow keys is a great way to force hands to the home row 2022-12-21 23:54:10 That said, I do eventually want to support the arrow keys, but to get there I plan to add a more sophisticated keyboard interface that's polled. 2022-12-21 23:54:17 With a timer tick interrupt. 2022-12-21 23:54:35 I've got that "tick" mechanism in, but haven't used it for keyboard stuff yet. 2022-12-21 23:56:11 I do that by having NEXT decrement a register that holds a tick count. When it reaches zero, NEXT jumps off and does something else. I set tick to one million, so aside from adding one dec instruction and one conditional branch (not taken most of the time), it has no particularly noticeable effect on system speed. 2022-12-21 23:56:17 there is a nice library that mimics gnu readline, except that the library is written in c 2022-12-21 23:56:24 Same mechanism will be used for multi-tasking. 2022-12-21 23:56:43 Background words and so on. 2022-12-21 23:57:09 KipIngram: that's a nice trick to avoid using a clock interrupt 2022-12-21 23:57:10 It's all going to be cooperative, though - background words have to be written to relenquish control after a short period - otherwise you'll notice foreground delays. 2022-12-21 23:57:42 It was one of those things that was "obviously easy to do," so I popped it in. 2022-12-21 23:58:00 so background words have to do a short increment of work and have no net stack effect. 2022-12-21 23:58:17 There isn't any sort of "context switch" here - it uses the same stack the foreground is using. 2022-12-21 23:59:07 Eventually I want to have a looped list of background words - each time background gets called it will cycle to the next one. 2022-12-21 23:59:16 And an easy way to manipulate that list. 2022-12-21 23:59:26 Put items in, take them out, pause items, etc.