2022-12-31 01:39:03 <KipIngram   > Ah, Icarus Verilog + GTKWave is COOL.
2022-12-31 11:13:19 <KipIngram   > Groovy - I got the input and output byte swapping wrapped around a ram model, and so far that seems to work.  Only lightly tested so far, but I successfully wrote a 32-bit cell and then read it back byte by byte.
2022-12-31 11:16:31 <KipIngram   > The ram itself isn't right yet - I'll do that in the end with 32 individual 1-bit wide RAMs, but I figured the simulations will be a lot faster if I use a 32-bit wide module.
2022-12-31 11:17:12 <KipIngram   > On to instruction fetching.
2022-12-31 15:53:28 <KipIngram   > Ok, I'm not doing this quite precisely the way I expected to.  What I thought I would do is instantiate specific logical constructs, from those available in the Xilinx portfolio, explicitly, and wire them together using Verilog.
2022-12-31 15:53:56 <KipIngram   > But that's a damn tedious thing to do - even after I know exactly what I want, just constructing is a slow and painful job.
2022-12-31 15:54:40 <KipIngram   > So I'm taking kind of a hybrid approach.  I'm doing the design the way I've always done it - work it out on paper with those specific constructs in mind.  So that I know what CAN be done in terms of timing and so on.
2022-12-31 15:55:15 <KipIngram   > Then I've decided to be willing to let the synthesizer help with the actual implementation - it's a lot less work to write things out that way.
2022-12-31 15:56:29 <KipIngram   > Then I'm pulling it into the Xilinx software and synthesizing it, and LOOKING at the resulting circuit.  So long as I get more or less what I had envisioned, I'm happy.  But if something comes in looking a lot more costly than I expected it to, I'll roll up my sleeves and figure that out - figure out how to get it to do what I want.
2022-12-31 15:57:58 <KipIngram   > I've more or less begin on it now, and so far that seems to be working out fine.  I did the byte swapping bits (both sides) that way last night, and when I opened it up and looked it looked pretty much exactly as I expected.
2022-12-31 16:00:55 <KipIngram   > The other big payoff of doing it this way is that I'm not just nailing it totally to Xilinx; the Verilog I'm writing should be vendor portable, and that's a big payoff.