2023-06-29 11:48:04 <KipIngram   > Forth doesn't usually have conditional operations other than jump.  There is ?dup which is a "conditional dup," but that's usually the only one.
2023-06-29 11:48:19 <KipIngram   > For other things (like conditional OR) you have to write code around it.
2023-06-29 15:04:31 <FUZxxl      > ?dup is a nightmare for any register allocator
2023-06-29 15:37:24 <KipIngram   > Yeah, and a nightmare for a lot of "smart compiler" thins.  Anything that makes it impossible for the compiler to know the state of the stack (i.e., for the stack state to be DATA dependent) is a pain.
2023-06-29 16:57:08 <MrMobius    > A lot of normal Forth code causes the optimizer to choke
2023-06-29 16:57:21 <MrMobius    > IF 5 THEN
2023-06-29 16:57:43 <MrMobius    > and you have to spill
2023-06-29 17:59:51 <KipIngram   > Poor guy on Quora asks if there's any proof of the simulation hypothesis, because "it's giving him an existential crisis."
2023-06-29 18:00:04 <KipIngram   > His English wasn't quite that correct, but I assume it's a second language for him.
2023-06-29 18:00:27 <KipIngram   > Which puts him ahead of me even if it's stilted English, because I don't have a second language.
2023-06-29 18:02:14 <KipIngram   > I have little use for the simulation hypothesis.  No, there's zero proof of it, and it doesn't even win from an Occam's Razor perspective either.
2023-06-29 18:02:23 <KipIngram   > It adds complication to your required model.
2023-06-29 18:54:27 <KipIngram   > MrMobius: that's the reason the ARM goes heavy into conditional execution, isn't it?  So you can keep your pipeline flowing more smoothly?
2023-06-29 18:55:53 <KipIngram   > I didn't realize untils just a few weeks ago that x64 has a set of conditional instructions.
2023-06-29 19:05:23 <remexre     > some of the newer RISC-V cores are doing funny things with recognizing when a sequence of instructions with a branch could be done with conditional instructions instead, and emitting conditional uops instead
2023-06-29 19:06:30 <remexre     > ( https://patchwork.ozlabs.org/project/gcc/patch/20190430234741.8120-1-jimw@sifive.com/ )