2023-07-15 01:32:37 <remexre     > If you're doing remote blocks, have you thought about doing transactional memory with them? Complicates the implementation quite a bit, but I've found it convenient in other languages, and I think you can keep the BLOCK/@/! interface without giving yourself migraines when you want threads or devices to be concurrently accessing remote storage
2023-07-15 08:21:38 <KipIngram   > I don't at the moment see how that would "fit into" my design.
2023-07-15 08:22:50 <KipIngram   > If I run just a single fiber, then any sequence of primitives (no : definitions) will be atomic.  But the minute I have multiple fibers that's no  longer guaranteed.
2023-07-15 08:27:56 <KipIngram   > I'm not sure I see how I'd implement the transactional business.  On the other hand, locks aren't too hard.
2023-07-15 08:28:25 <KipIngram   > These days there are always instructions designed specifically to let you do that.
2023-07-15 08:35:48 <KipIngram   > Looks like transactional support in hardware has been kind of spotty.  Intel offered something but then later removed it.
2023-07-15 10:25:05 <KipIngram   > You know, it wouldn't be hard at all to implement an F18A style vm.  Not sure how it would perform relative to other approaches, but it would be pretty straightforward.
2023-07-15 10:25:22 <KipIngram   > Adjusted slightly, to account for not having hardware customization available.
2023-07-15 10:25:57 <KipIngram   > And I think I'd find the five bit opcodes a bit confining - I'd be inclined toward six, I think.
2023-07-15 10:26:32 <KipIngram   > And 32-bit cells rather than 18.
2023-07-15 10:27:10 <KipIngram   > Also, I'd work from the least significant end of the cells up, rather than from most significant down.
2023-07-15 10:37:05 <KipIngram   > Core code would look something like this:
2023-07-15 10:37:07 <KipIngram   > https://paste2.org/94b28fDO
2023-07-15 10:37:45 <KipIngram   > rbx would point to a table of code locations for the instructions.
2023-07-15 10:38:14 <KipIngram   > Eventually you will wind up getting zero for your six bits - that one gets used to move you to the next instruction cell.
2023-07-15 10:39:58 <KipIngram   > Actually this would be better, and doesn't consume an instruction code:
2023-07-15 10:39:59 <KipIngram   > https://paste2.org/92Zt0gte
2023-07-15 10:40:14 <KipIngram   > Oh, well, yeah, it still does consume the zero code.
2023-07-15 10:40:19 <KipIngram   > But it's likely faster.
2023-07-15 10:40:33 <KipIngram   > I don't know - probably close to the same.  I'd have to measure.
2023-07-15 10:40:52 <KipIngram   > I lean toward the first one.
2023-07-15 10:50:38 <KipIngram   > One thing I like about that is how clear it is what porting would involve.  Just write the instruction set, and your done.
2023-07-15 10:50:45 <KipIngram   > :-(  YOU'RE
2023-07-15 10:51:55 <thrig       > ur
2023-07-15 10:52:19 <KipIngram   > :-)  Actually that can mean either one, can't it?
2023-07-15 10:52:42 <thrig       > and! it pisses off the grammar nazis
2023-07-15 10:53:11 <KipIngram   > I saw something new yesterday.  Book I'm reading (Sandman Slim series) had "I would have" written as I'd've.
2023-07-15 10:53:23 <KipIngram   > Double contraction - I've never seen that in print before.
2023-07-15 10:53:29 <KipIngram   > But it was absolutely obvious what it meant.
2023-07-15 10:53:33 <thrig       > you'll hear it though
2023-07-15 10:53:41 <KipIngram   > Yes - I hear it all the time.
2023-07-15 10:53:56 <KipIngram   > So... why not?  I'm fine with it.
2023-07-15 10:54:37 <KipIngram   > That book I recommended a while back - The Unfolding of Language - contends that's how languages evolve to start with.  Through "grass roots inventions" of new ways of speaking and writing.
2023-07-15 10:54:51 <KipIngram   > And yes, all through history it has pissed off the language Nazis.
2023-07-15 10:55:22 <KipIngram   > Every generation you can find papers contending that the whole world's about to go into the crapper because of the idiotic way the people are talking.
2023-07-15 10:55:46 <KipIngram   > Imminent doom, over and over again.
2023-07-15 10:55:59 <thrig       > luckily some of those Roman papers included how people pronounced things, which is useful information
2023-07-15 10:56:11 <KipIngram   > Yeah.
2023-07-15 10:56:51 <KipIngram   > Saw a video where a guy recommended classical Latin as the best way to preserve your thoughts - he said in a thousand years it will mean the same thing it means now, BECAUSE it's a dead language and isn't evolving underneath you.
2023-07-15 10:57:00 <KipIngram   > Seems like a reasonable argument to me.
2023-07-15 10:57:32 <KipIngram   > Speaking off, I kind of set my Latin studies aside when I got to thinking about Forth again a few months back - I need to reengage with that.
2023-07-15 10:57:38 <thrig       > the best way is to become super popular so that folks copy and translate your words
2023-07-15 10:57:40 <KipIngram   > I felt like I was doing ok with it.
2023-07-15 10:58:00 <KipIngram   > But I probably ought to start at the beginning of the book again now.
2023-07-15 10:58:48 <KipIngram   > Well, they'd be interpreting your words too, through their contemporary cultural lens.
2023-07-15 11:00:45 <KipIngram   > Anyway, re: the F18A emulation, I'd go to six bits because I'd want to add some instructions.  I'd want my conditional returns (well, some of them, at least) and so on.
2023-07-15 11:01:01 <KipIngram   > The { ... } stuff, etc.
2023-07-15 11:02:25 <KipIngram   > I noticed that what's missing from the F18A instruction set is any sort of thread swap support.
2023-07-15 11:02:41 <KipIngram   > Looks like that capability is just absent.
2023-07-15 11:03:16 <KipIngram   > Maybe you could make it work somehow, but emptying the stacks into RAM seems like it would be a pain.
2023-07-15 11:06:59 <KipIngram   > Also, re: extending that instruction set, I think I'd want two opcodes for lit.  One would just take "the rest of the current cell" as the literal, and would probably cover most cases.  The other would take the next two 32-bit cells and would get you to full 64-bit literals.
2023-07-15 11:08:05 <KipIngram   > short_lit: push rax ; lodsd ; next.  long_lit: lodsq ; push rax ; lodsd ; next.
2023-07-15 11:08:53 <KipIngram   > Well, except TOS would be register cached, but along those lines at least.
2023-07-15 11:10:02 <KipIngram   > That whole approach might be faster because it's  executing several instructions before fetching more from RAM.
2023-07-15 11:18:37 <KipIngram   > And it's certainly compact.
2023-07-15 11:20:39 <veltas      > "but emptying the stacks into RAM seems like it would be a pain" for small stacks that doesn't sound too bad though
2023-07-15 11:21:02 <KipIngram   > Yes, and his stacks are small, and strictly limited.
2023-07-15 11:21:15 <KipIngram   > I imagine it could be done - I just didn't stare at it long enough.
2023-07-15 11:21:27 <veltas      > Conventional OS's would do this by just saving/setting SP and changing the virtual memory mapping
2023-07-15 11:21:53 <veltas      > Well not for threads within one process, map wouldn't change
2023-07-15 11:21:57 <KipIngram   > So, looking at the instruction set, it says that execute "swaps P and R."  That makes it look to me like you would need a >r before execute to get the same behavior we're accustomed to.
2023-07-15 11:21:58 <veltas      > So just saving/setting SP
2023-07-15 11:22:05 <KipIngram   > Right.
2023-07-15 11:22:09 <veltas      > And IP
2023-07-15 11:22:30 <KipIngram   > When you can play with the memory management hardware it becomes easier.
2023-07-15 11:24:24 <veltas      > Which you can with £1 SoC's
2023-07-15 11:28:02 <veltas      > Have been looking at the ESP8684H2, considering getting something like that and trying to play with it
2023-07-15 11:30:31 <veltas      > Well actually I'm not sure what MMU features it has, a similar chip seemed to support access protection features though
2023-07-15 12:24:30 <veltas      > Okay that chip doesn't have it but another one with a similar name does :)
2023-07-15 12:24:33 <veltas      > I don't need it anyway
2023-07-15 12:40:54 <KipIngram   > Yeah, that's  my main misgiving about investing a lot of work in a "Linux capable" memory management system.  Linux *doesn't* offer me access to all that stuff, and therefore anything I put together will just be "not appropriate" when I get to situations where I do have that access.
2023-07-15 12:41:15 <KipIngram   > Doesn't stop me from wanting something I can run under Linux, though.
2023-07-15 13:34:07 <KipIngram   > So, P is the program counter on F18A, isn't it?
2023-07-15 13:34:45 <KipIngram   > What's the use of the !p instruction?  That's commented as "store via P, auto-increment P."
2023-07-15 13:34:59 <KipIngram   > That reads as though it's storing into the code stream.
2023-07-15 13:37:33 <KipIngram   > There's no SWAP instruction.
2023-07-15 13:56:31 <KipIngram   > I'm feeling a temptation to watch some of the early Supernatural episodes again.  It's been a while.
2023-07-15 13:56:57 <KipIngram   > It's one of the few shows I regarded as worth owning on Bluray.
2023-07-15 14:00:28 <Zarutian_iPad> KipIngram you can execute instructions directly from a comm port
2023-07-15 14:01:19 <Zarutian_iPad> iff P is pointing to a commport then the autoincrement is suppressed
2023-07-15 14:04:54 <Zarutian_iPad> hence you can have an instruction cell with @p to_a @a !p on a commport that does PEEK basically
2023-07-15 14:06:35 <Zarutian_iPad> I think one of the programs on green array site demonstrates that. Called snorkel or some such
2023-07-15 19:09:49 <KipIngram   > Ah.  Ok, that makes sense.  I saw no use of it executing code, but that solves the riddle.
2023-07-15 19:09:51 <KipIngram   > Thanks.
2023-07-15 22:27:36 <MrMobius    > doesn't it have a memory pointer register?