2023-09-30 19:24:46 I'm starting to sketch out a way to manage the 32655 flash in a "wear leveling" friendly way. 2023-09-30 19:26:23 Basically I want a design that lets me just "write my way through" the flash, one writeable item at a time. Then when I've used it all up I'll start over. But any way you slice it, when I power on I need a smidge of information to "get oriented," and that needs to come from a uniform place. 2023-09-30 19:27:04 32655 is a 512KibiX8 flash memory that conforms to JEDEC pinout standard? 2023-09-30 19:27:15 So I think I'll use a single page to provide that. On each power down, I'll write this critical piece of information to the next 128-bit word of that page. And on power up I'll scan and use the last non-zero item, which will be the one I wrote last. 2023-09-30 19:27:31 And I won't erase that page until I've completely used it up, which will be 512 power cycles. 2023-09-30 19:28:04 The Max32655 is a system on a chip which contains an internal 512kB flash. 2023-09-30 19:28:40 From what I can tell rerading the docs, I erase it in 8kB pages and write it in 128 bit words. 2023-09-30 19:28:54 And read it any way I want to - the entire thing is mapped into the address space. 2023-09-30 19:29:34 oh, I see I was going to recommend fram or memresitive chips I been seeing on digikey when doing parametric search for non-volatile memories 2023-09-30 19:29:38 So that one page I use as I just described will be the only page that must reside at an unchanging location. 2023-09-30 19:29:56 I'm going to arrange for everything else to be "mappable." 2023-09-30 19:30:03 To support the wear leveling plan. 2023-09-30 19:30:40 Thanks, but that's not quite the situation. I've read some nice things about those chips, though. 2023-09-30 19:31:03 My flash is rated at 10k program/erase cycles. 2023-09-30 19:32:31 So that would mean I'd expect that one special page to last for 512*10k > five million power cycles. 2023-09-30 19:32:44 Ought to cover me. :-)