2021-07-31 17:05:00 <john_ceph   > Hi
2021-07-31 17:19:12 <john_ceph   > crc: I've been looking at napia, looks pretty nice. I am a bit confused about interrupt handling though.
2021-07-31 17:24:52 <john_ceph   > Currently the active core state is backed up at bundle granularity. If an interrupt could be triggered in the middle of a bundle (or even in the middle of a single instruction), this would break things when returning.
2021-07-31 17:26:23 <crc         > this is something I need to look at further. I've been hampered a bit but not having an assembler for napia so far, but that'll be resolved soon
2021-07-31 17:27:17 <john_ceph   > This brings me to my questions:
2021-07-31 17:27:22 <john_ceph   > 1) If a hardware interrupt is triggered by an interface (possibly completely asynchronously), will the VM cache it and handle it at the end of the cycle?
2021-07-31 17:28:05 <crc         > that is my current plan
2021-07-31 17:28:56 <john_ceph   > 2) If a core triggers a software interrupt (using the ti opcode), will it complete the current bundle before the interrupt is triggered?
2021-07-31 17:31:30 <crc         > anything after `ti` in a bundle is ignored (as with `ca`, `cc`, `ju`, `cj`, and `re`)
2021-07-31 17:31:53 <crc         > [this will be detailed in the revised spec I'm working on]
2021-07-31 17:36:47 <john_ceph   > Hm, if the stack guard is triggered, the execution will go back to the broken core at the end of the ISR, even if the core has been disabled.
2021-07-31 17:38:45 <john_ceph   > The broken core will execute its next instruction bundle, potentially corrupting working memory of other cores, no matter what.
2021-07-31 17:38:51 <crc         > yes. this may be less than ideal
2021-07-31 17:39:17 <crc         > 
ACTION expects it to take a while to work out handling the interrupts and recovery model

2021-07-31 17:40:55 <john_ceph   > All in all, it looks exciting. Looking forward to seeing it in action.
2021-07-31 17:43:21 <john_ceph   > By the way, what is the reasoning behind limiting half-word accesses to not cross word boundaries?
2021-07-31 17:46:16 <crc         > Internally this is still modeled as a 32-bit aligned system. Allowing reads & writes across boundaries complicates that. This is only really an issue with instruction processing; if you attempt to span a word boundary with a 16-bit inline literal.
2021-07-31 17:47:29 <crc         > I might relax the rule in general, but document that values within a bundle (and bundles in general) must remain within a word. Still undecided on this.
2021-07-31 17:52:06 <crc         > (the read/write half functions should already allow for this, but I haven't actually tested that yet)
2021-07-31 17:55:15 <john_ceph   > Mmh, lb and lh over bundle boundaries would break things.