2026-09-08 03:02:45 <xentrac     > iv4nshm4k0v: that's an interesting idea!  One usual approach is to reject the code until the end of the line, giving an error message instead of the conventional " ok\r\n"
2026-09-08 03:04:28 <xentrac     > I'm excited to report that I have https://github.com/kragen/calculusvaporis simulating successfully in Verilog and synthesized to an FPGA bitstream to load onto an iCE40UP5K FPGA; nextpnr thinks it can run at 57.68 MHz
2026-09-08 03:04:55 <xentrac     > it's a pretty Forthish CPU, but I have to admit that it doesn't have two stacks; it only has one
2026-09-08 03:08:49 <xentrac     > here's a simple multiplication program: http://canonical.org/~kragen/tmp/mul.cv
2026-09-08 03:12:43 <xentrac     > it produces the correct answer (an asterisk, ASCII character 42) in the two Python simulators and the Verilog simulator
2026-09-08 03:15:49 <xentrac     > the CPU alone is 105 4-LUTs, which is smaller than Lattice's smallest FPGA, but it also uses 6 block RAMs, which are missing on that FPGA
2026-09-08 03:19:48 <xentrac     > configured to use an on-chip RAM for its program/data memory (it's a von Neumann machine) it uses 181 4-LUT logic cells, which is still pretty tiny but almost as big as SeRV
2026-09-08 04:42:55 <xentrac     > I've been thinking about adding a second stack to it, in RAM.  It currently has a 2-item operand stack, and the jump/call/tc/jalr instruction swaps the PC with the top of stack, so the callee can store it in a memory location if it wants to
2026-09-08 04:44:40 <xentrac     > a 2-item stack sounds horrible, but it's almost the same as normal assembly-language programming.  Instead of `add r1, r2, r3` you have `$r2 @ $r3 @ - $r1 !`
2026-09-08 04:45:05 <xentrac     > I should say instead of `sub r1, r2, r3`.  I'm thinking about adding addition to it